The typical arrangement for use of synchronous microprocessors is to have both microprocessors run the same program asynchronously and then compare their results at the end of each task. After presenting its operating results to a comparison circuit the faster microprocessor waits for a period of time while the slower microprocessor presents its operating results to the comparison circuit. Thus, the microprocessors are not actually running in synchronism, but rather, the microprocessors are continuously resynchronized after a predetermined number of operations.
The present invention enables two microprocessors to actually run synchronously with their address, data and status bits being compared during each bus cycle.